Digital Circuit Reliability Session
Session Type: Lecture
Session Code: A3L-E
Location: Room 5
Date & Time: Monday December 12, 2016 (15:30 - 17:10)
Chair: Mathieu Thevenin

 

    Papers are listed in the order they will be presented.

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Paper
Id
TopicTitle/Author
3072 1 Electromagnetic Security Tests for SoC
Fabien Majéric, Eric Bourbao, Lilian Bossuet
3242 1 ECC Module Optimization for Storage Transient Error-Tolerant ASICs
Keisuke Inoue
3061 1 Investigating the Efficiency and Accuracy of a Data Type Reduction Technique for Soft Error Analysis
Ghaith Kazma, Ghaith Bany Hamad, Otmane Ait Mohamed, Yvon Savaria
3113 1 Impact Evaluation of Logic Blocks Configuration on FPGA's Soft Error Rate Estimation
Fábio Batagin Armelin, Lírida A. B. Naviner, Roberto d'Amore, Irany...
3036 1 Extending the Viability of Power Signature – Based IP Watermarking in the SoC Era
George Blanas, Haridimos Vergos