Data Converters IV Session
Session Type: Poster
Session Code: B3P-P
Location: Salle de bal est
Date & Time: Tuesday May 24, 2016 (14:30 - 16:00)
Chair: Joao Goes



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1361 1.5 A Pipeline ADC for Very High Conversion Rates
Dante Gabriel Muratore, Edoardo Bonizzoni, Franco Maloberti
1430 1.5 Spatially Interleaved Architecture for High-Frequency Data Converters
Baptiste Grave, Amin Arbabian
1988 1.5 A 10-Bit Asynchronous SAR ADC with Scalable Conversion Time in 0.18µm CMOS
Po-Chiang Tung, Duen-Ting Fan, Tsung-Heng Tsai
1888 1.5 An Ultra-Low Voltage, VCO-Based ADC with Digital Background Calibration
Neelakantan Narasimman, Tony Tae-Hyoung Kim
1293 1.5 A PVT-Tracking Metastability Detector for Asynchronous ADCs
Yung-Hui Chung, Chia-Wei Yen
1623 1.5 A Low Power Low Latency Comparator for Ramp ADC in CMOS Imagers
Amandeep Kaur, Mukul Sarkar
1970 1.5 A Flexible Receiver Using Delta-Sigma Modulation
Minh Tien Nguyen, Chadi Jabbour, Van Tam Nguyen
1460 1.8 Low-Cost Dithering Generator for Accurate ADC Linearity Test
Yan Duan, Tao Chen, Degang Chen
1103 1.5 An on-Chip Para-C Calibration Architecture for Successive Approximation ADC
Yaguang Zhu, Jie Yuan
1267 1.5 A 12-Bit SAR ADC with Background Self-Calibration Based on a MOSCAP-DAC with Dynamic Body-Biasing
Taimur Rabuske, Jorge Fernandes
1370 1.5 A Digital Calibration Technique for Wide-Band CT MASH Sigma-Delta ADCs with Relaxed Filter Requirements
Chenming Zhang, Lucien J. Breems, Georgi Radulov, Muhammed Bolatkal...
1927 1.5 A Novel Autocorrelation-Based Timing Mismatch Calibration Strategy in Time-Interleaved ADCs
Xiao Wang, Fule Li, Zhihua Wang
1024 1.5 High-Level Optimization of Sigma-Delta Modulators Using Multi-Objetive Evolutionary Algorithms
Manuel Velasco-Jiménez, Rafael Castro-López, Jose M de la Rosa
1150 1.5 Using to Rapidly Obtain ELD Compensated CT Sigma-Delta Modulators
Johannes Wagner, Rudolf Ritter, Maurits Ortmanns
1426 1.5 Noise-Cancelling Sturdy MASH Delta-Sigma Modulator
Changsok Han, Ahmed Fahmy, Nima Maghari
1459 1.5 Multi-Stage Delta-Sigma Modulator with a Relaxed Opamp Gain Using a Back-End Digital Integrator
Changsok Han, Taewook Kim, Arun Javvaji, Nima Maghari
1465 1.5 Gm-Cell Nonlinearity Compensation Technique Using Single-Bit Quantiser and FIR DAC in Gm-C Based Delta-Sigma Modulators
Debajit Basak, Kong-Pang Pun