VLSI VI Session
Session Type: Poster
Session Code: C3P-W
Location: Salle de bal est
Date & Time: Wednesday May 25, 2016 (14:30 - 16:00)
Chair: Yuan-Hao Huang,
Lan-Da Van



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1419 12.14 Generating Voltage Drop Aware Current Budgets for RC Power Grids
Zahi Moudallal, Farid Najm
1568 12.14 Crosslink Insertion for Minimizing OCV Clock Skew
Kiwon Yoon, Seongbo Shim, Youngsoo Shin
1811 12.14 Top-Level Activity-Driven Clock Tree Synthesis with Clock Skew Variation Considered
Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou
2299 12.14 Exploiting Useful Skew in Gated Low Voltage Clock Trees
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
1680 12.3 Efficient Traffic Balancing for NoC Routing Latency Minimization
João Ferreira, Jarbas Silveira, Jardel Silveira, Rodrigo Cataldo, T...
1708 12.3 Temperature-Aware Task Scheduling Heuristics on Network-on-Chips
Shan Cao, Zoran Salcic, Yingtao Ding, Zhaolin Li, Shaojun Wei, Xian...
1948 12.3 High Performance 3D CMP Design with Stacked Hybrid Memory Architecture in the Dark Silicon Era Using a Convex Optimization Model
Salman Onsori, Arghavan Asad, Kamraan Raahemifar, Mahmood Fathy
2213 12.3 Towards Efficient and Concurrent FFTs Implementation on Intel Xeon/Mic Clusters for LTE and HPC
Mounir Khelifi, Daniel Massicotte, Yvon Savaria
2326 12.3 Synchronously Triggered GALS Design Templates Leveraging QDI Asynchronous Interfaces
Waqas Gul, Syed Rafay Hasan, Osman Hasan, Faiq Khalid Lodhi, Falah ...