VLSI IV Session
Session Type: Poster
Session Code: A3P-W
Location: Salle de bal est
Date & Time: Monday May 23, 2016 (14:30 - 16:00)
Chair: Meng-Fan Chang,
Chuan Zhang



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1480 12.1 A Novel Fast, Low-Power and High-Performance XOR-XNOR Cell
Majid Amini Valashani, Sattar Mirzakuchaki
1907 12.1 Area-Efficient and Low Stand-by Power 1K-Byte Transmission-Gate-Based Non-Imprinting High-Speed Erase (TNIHE) SRAM
Weng-Geng Ho, Kyaw Zwa Lwin Ne, Nagarajan Prashanth Srinivas, Kwen-...
2031 12.0 A Reduced Hardware Complexity Data-Weighted Averaging Algorithm with No Tonal Behavior
Alberto Celin, Andrea Gerosa
2056 12.2 Implementation of Efficient Parallel Discrete Cosine Transform Using Stochastic Logic
Yan Li, Jianhao Hu, Jie Chen
1326 12.18 Class D CMOS Power Amplifier with On/Off Logic for a Multilevel Outphasing Transmitter
Mikko Martelius, Kari Stadius, Jerry Lemberg, Tero Nieminen, Enrico...
1335 12.5 Intra Mode Power Saving Methodology for CGRA-Based Reconfigurable Processor Architectures
Narasinga Rao Miniskar, Rahul R Patil, Raj Narayana Gadde, Young-Ch...
1350 12.5 A 16-Valued Logic FPGA Architecture Employing Analog Memory Circuit
Renyuan Zhang, Mineo Kaneko
1662 12.11 SiGe HBT X-Band and Ka-Band Switchable Dual-Band Low Noise Amplifier
Panglijen Candra, Tian Xia
1738 12.12 An Energy-Efficient Subthreshold Level Shifter with a Wide Input Voltage Range
Yuan Cao, Wenbin Ye, Xiaojin Zhao, Peigang Deng
1839 12.12 Design of an Optimized Reversible Bidirectional Barrel Shifter
Sadia Nowrin, Lafifa Jamal, Hafiz Md. Hasan Babu
2024 12.12 Luminance-Adaptive Smart Video Storage System
Jonathon Edstrom, Dongliang Chen, Jinhui Wang, Huan Gu, Enrique Alv...
2125 12.13 Robust Near-Threshold Inverter with Improved Performance for Ultra-Low Power Applications
Md Shazzad Hossain, Ioannis Savidis