Oscillators & PLLs I Session
Session Type: Lecture
Session Code: C4L-H
Location: Salon Musset
Date & Time: Wednesday May 25, 2016 (16:00 - 17:30)
Chair: Elena Blokhina


    Papers are listed in the order they will be presented.

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1096 8.1 A Novel Low-Power and High-Speed Dual-Modulus Prescaler Based on Extended True Single-Phase Clock Logic
Song Jia, Ziyi Wang, Zijin Li, Yuan Wang
1849 8.1 A Power Efficient PLL with in-Loop-Bandwidth Spread-Spectrum Modulation Scheme Using a Charge-Based Discrete-Time Loop Filter
Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon
1900 8.1 A High-Q Spiral Inductor with Dual-Layer Patterned Floating Shield in a Class-B VCO Achieving a 190.5-dBc/Hz FoM
Chee Cheow Lim, Harikrishnan Ramiah, Jun Yin, Pui In Mak, Rui P. Ma...
2074 8.1 Sub-Picosecond-Jitter Clock Generation for Interleaved ADC with Delay-Locked-Loop in 28nm CMOS
Jianping Gong, Sulin Li, John McNeill
2118 8.1 A 24GHz Digitally Controlled Oscillator for Automotive Radar in 65nm CMOS
Iman Taha, Mitra Mirhassani